Python jobs in Düsseldorf

About this opportunity:

Are you passionate about driving innovation and working on pioneering 5G and 6G mobile communication solutions? Do you thrive in a flexible working culture, where new ideas are fostered and you are encouraged to develop new skills?

Then join Ericsson and our growing team in Rosenheim, Germany. The position as ASIC DSP Architect is located in Standards & Technology. Our purpose is early phase technology development targeting future generation radio products.

• Work on the forefront of technology, researching novel signal processing concepts and compute-architectures targeting Ericsson’s industry leading radio ASICs of the future
• Take on responsibility for concept exploration, architecture development and proof of concept implementation to deliver superior technical solutions while balancing power and cost/area tradeoffs
• Behavioral modelling of microarchitectures using System Verilog, C++, MATLAB
• RTL design, synthesis, RTL and gate level simulation using the latest EDA tools from Synopsys and Cadence
• Design constraining and design optimization including STA and timing closure in cooperation with our back-end experts
• Influence and advanced our design methodology and thereby continuously improve our way-of-working
• Work-flow automation using Python, TCL and shell scripts
• Secure IPR
• Interface and coordinate with multi-functional groups throughout Ericsson organization worldwide
• As a senior member of the team, you will coach and mentor junior members of the team and lead on technical level

• Master degree or equivalent in Electrical Engineering, Computer Science or a related field
• 7+ years of professional experience in the field of digital ASIC design including a track record in delivering high-quality, high performance, low-power signal processing implementations
• Proven experience in independently driving micro-architecture exploration activities for complex signal processing IP
• Solid background in digital signal processing
• Profound understanding of ASIC technology and industry trends
• A track record in low power ASIC design and familiarity with low power design techniques including clock and power gating (UPF)
• Ability to expertly balance and rationalize design tradeoffs especially in terms performance/power/area
• Strong proficiency in multiple areas of digital ASIC design flow: concepts and architecture, behavioral modeling, RTL design and optimization, verification, synthesis, timing analysis, power analysis, CDC, RDC
• Sound handling of powerful ASIC design and analysis tools (Candence/Synopsys) including good scripting skills (Python, TCL, shell scripting, MATLAB)
• Excellent proficiency in hardware description languages (VHDL, Verilog/ System Verilog)
• Complementary experience in back-end design is beneficial
• High proficiency in spoken and written English
• Strong analytical skills and a structured work approach
• Team spirit

At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.